Model simulation provides a mechanism by which the design of a component (e.g., the design of a hardware chip) can be tested prior to building the component. This testing is to ensure that the component, once built, will meet the desired specifications of the component. The component is tested by creating a model of the component and simulating the model. There are various types of model simulation, including event simulation and cycle simulation. Event simulation takes into account delays within the component (e.g., hardware delays), whereas cycle simulation ignores such delays.
Pervasive in the industry today are problems with simulating large and/or complex models. For example, there are problems associated with simulating the functionality of a complex Application Specific Integrated Chip (ASIC) using event simulation. In particular, as chip densities have increased, the performance of the simulation has degraded. That is, event simulators have experienced a non-linear increase in processing time, as the number of events have increased. Thus, as technology advances have steadily increased chip densities and more function has been placed on a chip (i.e., System On Chip (SOC)), an explosion in the number of events per cycle has been realized, as well as an increase in the simulation model size required to simulate a chip as a single entity.
Therefore, a need exists for a capability that facilitates simulation of these models. In particular, a need exists for a capability that enables the simulation of a model, such as the functionality of a chip, without degrading simulation performance. A need exists for a capability that enables the simulation of models within a distributed computing environment.